1. Field of the Invention
The present invention relates to a memory device and to a method of operation of such a memory device, and in particular to a mechanism for operating such a memory device when the access circuitry used to access the array of memory cells is operated from a peripheral voltage domain with a supply voltage less than the supply voltage in a core voltage domain used by the array of memory cells.
2. Description of the Prior Art
In modern data processing systems, it is becoming more and more common for certain parts of the data processing system to operate in a different voltage domain to one or more other parts. For example, a trend within integrated circuits is the increasingly common use of embedded memory, such as SRAM memory. With the reduction in size of process geometries, the individual memory cells within the memory are becoming less stable. To reduce the power consumption of the integrated circuit, it is desirable to reduce the operating voltage of the components within the integrated circuit. However, whilst this can be done for many of the components within the integrated circuit, including access logic circuitry associated with the memory device, it is often the case that a higher voltage is needed to drive the array of memory cells within the memory device in order to enhance the stability of those cells. Hence, embedded SRAM bit cells may use a higher voltage supply (providing a core voltage level) to guarantee state retention, whilst the rest of the system, including the access logic circuitry employed to access those bit cells within the memory device, may use a lower voltage supply (providing a peripheral voltage level) to reduce power consumption. In order to maintain performance, and reduce switching power, a level shifting mechanism is needed to pass signals between these different voltage domains.
FIG. 1 is a block diagram schematically illustrating a known memory device 10 where the access logic circuitry 20 of the memory device is provided in a first voltage domain operating with a first voltage supply providing a peripheral voltage level VDDP and a ground voltage level (not shown), whilst the array of bit cells 30 is provided in a second voltage domain operating with a second voltage supply providing a core voltage level VDDC and the ground voltage level. The core voltage level VDDC is higher than the peripheral voltage level VDDP. This enables the access logic circuitry 20 to operate with a reduced power consumption, whilst the array of bit cells 30 is operated at a voltage level sufficient to guarantee state retention.
The access logic circuitry 20 will receive a number of control signals over path 55, these control signals identifying write transactions, read transactions, the addresses of those transactions, etc. It will also receive over path 60 write data for write transactions to be performed within the array of bit cells 30, and will output over path 75 the read data resulting from read transactions performed within the array of bit cells 30. As will be understood by those skilled in the art, the access logic circuitry 20 will include a number of components, such as address latches, various stages of word line decoding circuitry to decode the address in order to generate appropriate word line enable signals to activate addressed rows within the array of bit cells 30, write data path logic circuits used to control the voltages on the bit lines within the array of bit cells during a write operation, and various read data path logic circuits for processing the data read out of the array of bit cells in response to a read operation. Accordingly, for write operations, a number of signals will be generated for issuing to the array of bit cells 30 (these signals being schematically illustrated by the arrow 65 in FIG. 1). In one known prior art approach, these signals are subjected to a level up shifting function 40 in order to convert the voltage of those signals from the lower voltage domain to the higher voltage domain. Similarly, any data read out from the bit cells 30 over path 70 is subjected to a level down shifting function 50 in order to convert the voltage levels from the higher (core) voltage domain to the lower (peripheral) voltage domain, before those signals are then subsequently processed by the access logic circuitry 20.
The level up shifting mechanism 40 is generally more problematic to implement than the level down shifting mechanism 50 (in fact in many instances no specific level down shifting circuitry may be required), since when performing level up shifting there is the potential for establishing various DC paths that can result in significant power consumption, and which may potentially create short circuit current paths.
When the voltage difference between the core voltage domain and the peripheral voltage domain is relatively small (for example up to 250 mV) it is not always necessary to level shift all of the control signals routed from the access logic circuitry to the bit cells, and read and write operations performed in respect of the bit cells will still operate correctly. However, in modern systems the voltage difference between the core voltage domain and the peripheral voltage domain is getting larger, and may for example be in the range of 400 mV. With such a large difference in the voltage domains, it has been found that level shifting of the control signals is required in order to ensure correct operation of the bit cells within the array when performing read and write operations. In particular, it has been found that the write margin can be insufficient unless such level shifting has been performed. Accordingly, when the difference between the core voltage domain and the peripheral voltage domain is of the order of 400 mV, it is known to perform level shifting on all of the control signals provided from the access logic circuitry to the bit cells. Whilst this ensures correct operation, it has a significant impact on the overall power consumption of the memory device.
Accordingly, it would be desirable to provide a memory device which operates correctly when the voltage difference between the core voltage domain and the peripheral voltage domain is relatively large (e.g. of the order of 400 mV), but with a reduced power consumption compared with the known prior art approach.